Mototsugu Hamada 研究室

主宰者：Mototsugu Hamada

東京大学

AI 要約（直近 5 年の研究成果）

本研究室は、人工知能処理を極めて低い消費電力で実現するためのハードウェア技術の開発に取り組んでいます。特に、従来のコンピュータアーキテクチャが必要とするメモリへのアクセスを最小限に抑え、神経回路のように計算と配線を一体化させた「ワイヤドロジック」と呼ぶ回路構造に着目しています。音声認識や画像分類などの機械学習タスクを、電池駆動の小型デバイスでも動作させることが目標です。主な研究手法として、超スパース（重みの大部分がゼロ）で軽量な神経回路モデルの設計と、それをFPGAやカスタムシリコンチップ上に効率よく実装するための技術開発が挙げられます。量子化による精度圧縮、重みの二値化・三値化、構造化枝刈りなど、複数の軽量化技術を組み合わせることで、限られたハードウェア資源で大規模なニューラルネットワークを動作させています。その結果として、音声コマンド認識や画像分類を非常に低いエネルギー消費で実現するプロセッサの開発に成功しています。また、3次元積層メモリやチップ間の無線通信インターフェースなど、関連する周辺技術の研究も進めており、IoT機器やエッジAIデバイスの実現に向けた実装基盤の構築を進めています。

※ AI（Claude）が、公開されている論文要旨から研究の問い・手法・主要な発見を事実情報として抽出・再構成して自動生成しています。誤りを含む可能性があるため、正確性は研究室公式情報でご確認ください。

外部リンク

研究成果（41 件）

[2026] A Wired-Logic and Near-Memory Hybrid Processor for General-Purpose Audio Inference Using a Self-Supervised Encoder
DOI: https://doi.org/10.1109/ojsscs.2026.3703368
[2025] A 83.7% Resource Reduced FPGA-based Wired-Logic DNN Processor by Using Mixed-Precision Module Embedding Into Non-Linear Function LUT
DOI: https://doi.org/10.1109/iscas56072.2025.11043837
[2025] A Coarse- and Fine-Grained LUT Segmentation Method Enabling Single FPGA Implementation of Wired-Logic DNN Processor
DOI: https://doi.org/10.1145/3658617.3698484
[2024] Analysis and Design of Coarse and Fine Segmented LUT Implementation for FPGA-Based Resource Efficient Wired-Logic DNN Processors
DOI: https://doi.org/10.1587/transele.2024lhp0002
[2024] A 28-nm 0.8M-weights/mm2 9.1-TOPS/mm2 SRAM-Based All-Analog Compute-In-Memory Using Fine-Grained Structured Pruning with Adaptive-Ranging ADC
DOI: https://doi.org/10.1109/esserc62670.2024.10719563
[2024] Introduction to the Special Issue on the 2023 Symposium on VLSI Circuits
DOI: https://doi.org/10.1109/jssc.2024.3357259
[2024] Efficient FPGA Resource Utilization in Wired-Logic Processors Using Coarse and Fine Segmentation of LUTs for Non-Linear Functions
DOI: https://doi.org/10.1109/iscas58744.2024.10558064
[2023] A183.4-nJ/Inference 152.8-μW 35-Voice Commands Recognition Wired-Logic Processor Using Algorithm-Circuit Co-Optimization Technique
DOI: https://doi.org/10.1109/lssc.2023.3334625
[2023] A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA
DOI: https://doi.org/10.1587/transele.2023lhp0001
[2023] A 10.7-µJ/Frame 88% Accuracy CIFAR-10 Single-Chip Neuromorphic Field-Programmable Gate Array Processor Featuring Various Nonlinear Functions of Dendrites in the Human Cerebrum
DOI: https://doi.org/10.1109/mm.2023.3315676

続きを表示（残り 31 件）

[2023] A 183.4nJ/inference 152.8μW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application
DOI: https://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185297
[2023] A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network
DOI: https://doi.org/10.1109/iscas46773.2023.10181427
[2023] Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS
DOI: https://doi.org/10.1109/tcsi.2023.3268772
[2023] A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS
DOI: https://doi.org/10.1145/3566097.3567941
[2023] A 12.8-Gb/s 0.5-pJ/b Encoding-Less Inductive Coupling Interface Achieving 111-GB/s/W 3D-Stacked SRAM in 7-nm FinFET
DOI: https://doi.org/10.1109/lssc.2023.3252607
[2023] A Deep Metric Learning-Based Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion
DOI: https://doi.org/10.1109/ojies.2023.3284014
[2022] mmWave-YOLO: A mmWave Imaging Radar-Based Real-Time Multiclass Object Recognition System for ADAS Applications
DOI: https://doi.org/10.1109/tim.2022.3176014
[2022] A 12.8-Gbps 0.5-pJ/b Encoding-less Inductive Coupling Interface Using Clocked Hysteresis Comparator for 3D-stacked SRAM in 7-nm FinFET
DOI: https://doi.org/10.1109/a-sscc56115.2022.9980775
[2022] A Low-power RFID with 100kbps Data Rate Employing High-speed Power Clock Generator for Complementary Pass-transistor Adiabatic Logic
DOI: https://doi.org/10.1109/icecs202256217.2022.9971064
[2022] A 1.2nJ/Classification 2.4mm2 Wired-Logic Neuron Cell Array Using Logically Compressed Non-Linear Function Blocks in 0.18undefinedm CMOS
DOI: https://doi.org/10.7567/ssdm.2022.k-5-02
[2022] Pixel Pitch Hybrid Bonding and Three Layer Stacking Technology for BSI Image Sensor
DOI: https://doi.org/10.1109/iitc52079.2022.9881305
[2022] 3D-Stacked SRAM Using Near-Field Wireless Communication
DOI: https://doi.org/10.5104/jiep.25.549
[2022] A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA using Non-Linear Neural Network
DOI: https://doi.org/10.1109/hcs55958.2022.9895600
[2022] A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers
DOI: https://doi.org/10.1109/hcs55958.2022.9895622
[2022] Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format
DOI: https://doi.org/10.1109/newcas52662.2022.9842091
[2022] A bonding-less 5-GHz RFID module using inductive coupling between IC and antenna
DOI: https://doi.org/10.35848/1347-4065/ac4ce2
[2022] A 5.2GHz RFID Chip Contactlessly Mountable on FPC at any 90-Degree Rotation and Face Orientation
DOI: https://doi.org/10.1109/asp-dac52403.2022.9712597
[2022] A 5-GHz 0.15-mm² Collision-Avoiding RFID Employing Complementary Pass-Transistor Adiabatic Logic With an Inductively Connected External Antenna in 0.18-μm CMOS
DOI: https://doi.org/10.1109/lssc.2022.3223079
[2022] 1.2 nJ/classification 2.4 mm2 asynchronous wired-logic DNN processor using synthesized nonlinear function blocks in 0.18 μm CMOS
DOI: https://doi.org/10.35848/1347-4065/acac38
[2022] A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver
DOI: https://doi.org/10.1109/jssc.2022.3224421
[2021] A 0.61-μJ/Frame Pipelined Wired-logic DNN Processor in 16-nm FPGA Using Convolutional Non-Linear Neural Network
DOI: https://doi.org/10.1109/ojcas.2021.3137263
[2021] A 16 nJ/Classification FPGA-Based Wired-Logic DNN Accelerator Using Fixed-Weight Non-Linear Neural Net
DOI: https://doi.org/10.1109/jetcas.2021.3114179
[2021] A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC
DOI: https://doi.org/10.1109/jssc.2021.3108820
[2021] A bonding-less 5-GHz RFID module using a 300um x 500um IC chip
DOI: https://doi.org/10.7567/ssdm.2021.l-2-04
[2021] An on-chip antenna with an area of 0.9 square millimeters for RFID applications in the 5.8 GHz – 24 GHz range
DOI: https://doi.org/10.23919/isap47053.2021.9391369
[2021] CA2 area detection from hippocampal microscope images using deep learning
DOI: https://doi.org/10.1109/mwscas47672.2021.9531735
[2021] A Physical Verification Methodology for 3D-ICs Using Inductive Coupling
DOI: https://doi.org/10.1109/edaps53774.2021.9657043
[2021] A 5-GHz 0.15-mm2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna
DOI: https://doi.org/10.1109/a-sscc53895.2021.9634815
[2021] A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System
DOI: https://doi.org/10.1587/transfun.2021vlp0001
[2021] Sub-10-μm Coil Design for Multi-Hop Inductive Coupling Interface
DOI: https://doi.org/10.1145/3394885.3431649
[2021] A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOS
DOI: https://doi.org/10.1145/3394885.3431642

科研費（0 件）

まだデータがありません（KAKEN 取り込み後に表示）。

所属学会・役職（0 件）

まだデータがありません（学会データ連携後に表示）。

AI 要約（直近 5 年の研究成果）

外部リンク

関連研究室(8 件)

研究成果（41 件）

科研費（0 件）

所属学会・役職（0 件）