Hideharu Amano 研究室

主宰者：Hideharu Amano

東京大学

AI 要約（直近 5 年の研究成果）

本研究室は、エッジコンピューティングおよび次世代コンピューティング基盤の実現を目指し、再構成可能なハードウェア技術を中心に研究を展開しています。特に、FPGA（プログラマブルロジックデバイス）やASIC（専用集積回路）の設計・製造技術に注力しており、低消費電力かつ高速な計算処理を実現するための実装手法を研究しています。主要な研究テーマとしては、複数のFPGAボードを並列接続して大規模な計算を行うマルチFPGAクラスタの開発があります。これらのシステムを音声信号処理、画像認識、量子回路シミュレーション、遺伝子配列解析など多様なアプリケーションに適用し、性能と消費電力のバランスを最適化する方法を検討しています。また、製造から設計までの時間短縮が課題であった半導体チップ製作を、最小限の工程で実現する新しい製造プラットフォームの開発も進めており、学生が短期間でチップ製作を経験できる教育基盤の構築にも取り組んでいます。さらに、磁性トンネル接合を用いた低消費電力フリップフロップの開発や、細粒度再構成可能ロジックの圧縮技術など、デバイスレベルからシステムレベルまで、多層的なアプローチで省電力かつ高性能な計算システムの実現を目指しています。

※ AI（Claude）が、公開されている論文要旨から研究の問い・手法・主要な発見を事実情報として抽出・再構成して自動生成しています。誤りを含む可能性があるため、正確性は研究室公式情報でご確認ください。

外部リンク

研究成果（68 件）

[2025] Can the Agile-Chip Platform Carve Out a Niche Between ASICs and FPGAs?
DOI: https://doi.org/10.1109/coolchips65488.2025.11018602
[2025] Agile Prototyping of AI Hardware LSIs Using Multi-Layer Aluminum Interconnects in a Minimal Fab Environment
DOI: https://doi.org/10.7567/ssdm.2025.a-6-04
[2025] An SoC Design and Fabrication Hands-On Educational Course within One Week Using Structured ASIC
DOI: https://doi.org/10.1109/iscas56072.2025.11043626
[2024] Agile-X: A Structured-ASIC Created With a Mask-Less Lithography System Enabling Low-Cost and Agile Chip Fabrication
DOI: https://doi.org/10.1109/tvlsi.2024.3486239
[2024] Applying Run-Length Compression to the Configuration Data of SLM Fine-Grained Reconfigurable Logic
DOI: https://doi.org/10.1587/transinf.2024edp7033
[2024] FPGA-based Low Power Acceleration of HARK Sound Source Localization
DOI: https://doi.org/10.1109/coolchips61292.2024.10531180
[2024] Power analysis of an optical interconnected FPGA cluster for roadside units
DOI: https://doi.org/10.1109/icce59016.2024.10444498
[2024] Power Optimized Design Framework for FPGA Clusters
DOI: https://doi.org/10.2197/ipsjtsldm.17.77
[2024] Advancing Applications of Robot Audition Systems: Efficient HARK Deployment with GPU and FPGA Implementations
DOI: https://doi.org/10.3390/chips4010002
[2024] Qu-Trefoil: Large-Scale Quantum Circuit Simulator Working on FPGA With SATA Storages
DOI: https://doi.org/10.1109/tc.2024.3521546

続きを表示（残り 58 件）

[2023] TCI Tester: A Chip Tester for Inductive Coupling Wireless Through-Chip Interface
DOI: https://doi.org/10.3390/jlpea13030048
[2023] Parallel Implementation of CNN on Multi-FPGA Cluster
DOI: https://doi.org/10.1587/transinf.2022edp7175
[2023] Low power implementation of Geometric High-order Decorrelation-based Source Separation on an FPGA board
DOI: https://doi.org/10.1109/coolchips57690.2023.10121954
[2023] A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops
DOI: https://doi.org/10.1109/tvlsi.2023.3237794
[2023] RT-libSGM: FPGA-Oriented Real-Time Stereo Matching System with High Scalability
DOI: https://doi.org/10.1587/transinf.2022edp7131
[2023] FPGA based Power-Efficient Edge Server to Accelerate Speech Interface for Socially Assistive Robotics
DOI: https://doi.org/10.1109/sii55687.2023.10039093
[2023] A cost/power efficient storage system with directly connected FPGA and SATA disks
DOI: https://doi.org/10.1109/mcsoc60832.2023.00016
[2023] Board Allocation Algorithm for the Resource Management System of FiC
DOI: https://doi.org/10.1109/mcsoc60832.2023.00040
[2023] A state vector quantum simulator working on FPGAs with extensible SATA storage
DOI: https://doi.org/10.1109/icfpt59805.2023.00041
[2023] Enormous-Scale Quantum State Vector Calculation with FPGA-accelerated SATA storages
DOI: https://doi.org/10.1109/icfpt59805.2023.00049
[2023] Power Analysis and Power Modeling of Directly-Connected FPGA Clusters
DOI: https://doi.org/10.1587/transinf.2023pap0009
[2023] Parallel Implementation of Vision Transformer on a Multi-FPGA Cluster
DOI: https://doi.org/10.1109/candar60563.2023.00020
[2023] A Multi-FPGA Implementation of FM-Index Based Genomic Pattern Search
DOI: https://doi.org/10.1587/transinf.2022edp7230
[2023] Optimized Two-Step Store Control for MTJ-Based Nonvolatile Flip-Flops to Minimize Store Energy Under Process and Temperature Variations
DOI: https://doi.org/10.1109/tvlsi.2023.3318468
[2022] A traffic-aware memory-cube network using bypassing
DOI: https://doi.org/10.1016/j.micpro.2022.104471
[2022] FPL Demo: An FPGA-IP Prototype Chip for MEC devices
DOI: https://doi.org/10.1109/fpl57034.2022.00083
[2022] A Scalable Body Bias Optimization Method Toward Low-Power CGRAs
DOI: https://doi.org/10.1109/mm.2022.3226739
[2022] A Message Passing Interface Library for High-Level Synthesis on Multi-FPGA Systems
DOI: https://doi.org/10.1109/mcsoc57363.2022.00017
[2022] Distance Aware Compression for Low Latency High Bandwidth Interconnection Network
DOI: https://doi.org/10.1109/mcsoc57363.2022.00063
[2022] Boosting the Performance of Interconnection Networks by Selective Data Compression
DOI: https://doi.org/10.1587/transinf.2022pap0005
[2022] The Implementation of a Hybrid Router and Dynamic Switching Algorithm on a Multi-FPGA System
DOI: https://doi.org/10.1587/transinf.2022pap0009
[2022] An FPGA off-loading of HARK sound source localization
DOI: https://doi.org/10.1109/candarw57323.2022.00057
[2022] Multi-board FPGA Implementation to Solve the Satisfiability Problem for Multi-Agent Path Finding in Smart Factory
DOI: https://doi.org/10.1109/candarw57323.2022.00034
[2022] An Implementation of a 3D Image Filter for Motion Vector Generation on an FPGA Board
DOI: https://doi.org/10.1109/candar57322.2022.00018
[2022] Dynamic Routing Reconfiguration for Low-Latency and Deadlock-Free Interconnection Networks
DOI: https://doi.org/10.1109/candar57322.2022.00023
[2022] Toward a training of CNNs on a multi-FPGA system
DOI: https://doi.org/10.1109/candarw57323.2022.00074
[2022] Optimal switching time to minimize store energy in MTJ-based flip-flops under process and temperature variations
DOI: https://doi.org/10.1109/norcas57515.2022.9934567
[2022] Reconfiguration Cost for Reconfigurable Computing Architectures
DOI: https://doi.org/10.1109/snpd-summer57817.2022.00019
[2022] RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA
DOI: https://doi.org/10.1145/3535044.3535045
[2022] Power Analysis of Directly-connected FPGA Clusters
DOI: https://doi.org/10.1109/coolchips54332.2022.9772675
[2022] Body Bias Control on a CGRA based on Convex Optimization
DOI: https://doi.org/10.1109/coolchips54332.2022.9772708
[2022] An efficient compilation of coarse-grained reconfigurable architectures utilizing pre-optimized sub-graph mappings
DOI: https://doi.org/10.1109/pdp55904.2022.00010
[2022] Optimizing Application Mapping for Multi-FPGA Systems with Multi-ejection STDM Switches
DOI: https://doi.org/10.1109/fpl57034.2022.00032
[2022] Weighted Least Square Filter for Improving the Quality of Depth Map on FPGA
DOI: https://doi.org/10.15803/ijnc.12.2_425
[2021] Parallel Implementation of CNN on Multi-FPGA Cluster
DOI: https://doi.org/10.1109/mcsoc51149.2021.00019
[2021] Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops
DOI: https://doi.org/10.1109/mcsoc51149.2021.00047
[2021] A Multi-Tenant Resource Management System for Multi-FPGA Systems
DOI: https://doi.org/10.1587/transinf.2021pap0005
[2021] Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System
DOI: https://doi.org/10.1587/transinf.2021pap0002
[2021] CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis
DOI: https://doi.org/10.1587/transinf.2021pap0006
[2021] An FPGA-Based Optimizer Design for Distributed Deep Learning with Multiple GPUs
DOI: https://doi.org/10.1587/transinf.2021pap0008
[2021] Resource-saving FPGA Implementation of the Satisfiability Problem Solver: AmoebaSATslim
DOI: https://doi.org/10.1109/icfpt52863.2021.9609882
[2021] M-KUBOS/PYNQ Cluster for multi-access edge computing
DOI: https://doi.org/10.1109/candar53791.2021.00020
[2021] Low-Latency High-Bandwidth Interconnection Networks by Selective Packet Compression
DOI: https://doi.org/10.1109/candar53791.2021.00015
[2021] Weight Least Square Filter for Improving the Quality of Depth Map on FPGA
DOI: https://doi.org/10.1109/candarw53999.2021.00056
[2021] Analysis of Resistance Distribution and Voltage Drop in Chips with Inductive Coupling Wireless Communication Interface
DOI: https://doi.org/10.1109/candarw53999.2021.00055
[2021] CASE: CNN Acceleration for Speech-Classification in Edge-Computing
DOI: https://doi.org/10.1109/ieeecloudsummit52029.2021.00018
[2021] Mapping-Aware Kernel Partitioning Method for CGRAs Assisted by Deep Learning
DOI: https://doi.org/10.1109/tpds.2021.3107746
[2021] Analytical Performance Estimation for Large-Scale Reconfigurable Dataflow Platforms
DOI: https://doi.org/10.1145/3452742
[2021] Remote Dynamic Reconfiguration of a Multi-FPGA System FiC (Flow-in-Cloud)
DOI: https://doi.org/10.1587/transinf.2020edp7165
[2021] A programming environment for multi-FPGA systems based on CyberWorkBench
DOI: https://doi.org/10.1145/3468044.3468049
[2021] GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph
DOI: https://doi.org/10.1145/3468081.3471122
[2021] Implementing VTA, a tensor accelerator on Flow-in-Cloud
DOI: https://doi.org/10.1145/3468081.3471121
[2021] Hybrid Network of Packet Switching and STDM in a Multi-FPGA System
DOI: https://doi.org/10.1109/coolchips52128.2021.9410322
[2021] Implementation of Versatile Tensor Accelarator (VTA) on the Flow-in-Cloud FPGA system
[2021] A Case for Low-Latency Network-on-Chip using Compression Routers
DOI: https://doi.org/10.1109/pdp52278.2021.00029
[2021] Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths
DOI: https://doi.org/10.1109/pdp52278.2021.00030
[2021] TCI Tester
DOI: https://doi.org/10.1145/3394885.3431660
[2021] An implementation methodology for Neural Network on a Low-end FPGA Board
DOI: https://doi.org/10.15803/ijnc.11.2_172

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AI 要約（直近 5 年の研究成果）

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関連研究室(8 件)

研究成果（68 件）

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