Masato Motomura 研究室

主宰者：Masato Motomura

東京工業大学

AI 要約（直近 5 年の研究成果）

要約はまだ生成されていません。

※ AI（Claude）が、公開されている論文要旨から研究の問い・手法・主要な発見を事実情報として抽出・再構成して自動生成しています。誤りを含む可能性があるため、正確性は研究室公式情報でご確認ください。

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研究成果（63 件）

[2026] Efficient Vision Transformers via Token Merging with Head-Wise Attention Correction
DOI: https://doi.org/10.1109/wacv61042.2026.00381
[2026] AQPIM: Breaking the PIM Capacity Wall for LLMs with in-Memory Activation Quantization
DOI: https://doi.org/10.1109/hpca68181.2026.11408452
[2026] Annealed Mean Field Descent Is Highly Effective for Quadratic Unconstrained Binary Optimization
DOI: https://doi.org/10.1109/tevc.2026.3690973
[2026] Memory-Efficient and Trustworthy Neural Networks via Random Seed-Based Design
DOI: https://doi.org/10.1109/access.2026.3659474
[2026] The Strong Lottery Ticket Hypothesis for Multi-Head Attention Mechanisms
DOI: https://doi.org/10.1609/aaai.v40i29.39648
[2026] WhiteDwarf: A Holistic Co-Design Approach to Ultra-Compact Neural Inference Acceleration
[2026] A 22nm Continual Learning Accelerator for Autonomous Systems with 69.2TOPS/W Dynamic-Sparse-Weight-Updat and Dual-Mode Vector-Scaled-INT4 Processing
DOI: https://doi.org/10.1109/cicc65509.2026.11509530
[2025] DMSA: An Efficient Architecture for Sparse–Sparse Matrix Multiplication Based on Distribute-Merge Product Dataflow
DOI: https://doi.org/10.1109/tvlsi.2025.3558895
[2025] TTF-GNN: Memory-Efficient GNNs via Tensor Train Decomposition and Network Folding
DOI: https://doi.org/10.1109/coolchips65488.2025.11018558
[2025] Derek Chiou
DOI: https://doi.org/10.1109/mm.2025.3544666

続きを表示（残り 53 件）

[2025] <i>WhiteDwarf</i>: A Holistic Co-Design Approach to Ultra-Compact Neural Inference Acceleration
DOI: https://doi.org/10.1109/access.2025.3568916
[2025] BingoGCN: Towards Scalable and Efficient GNN Acceleration with Fine-Grained Partitioning and SLT
DOI: https://doi.org/10.1145/3695053.3731115
[2025] Amorphica: A Fully Connected Annealer Supporting Metamorphic Annealing and Scalable Multi Chip Integration
DOI: https://doi.org/10.1109/access.2025.3620896
[2025] Trustworthy Deep Learning Acceleration with Customizable Design Flow Automation
DOI: https://doi.org/10.1145/3728179.3728198
[2024] A GPU-Based Ising Machine With a Multi-Spin-Flip Capability for Constrained Combinatorial Optimization
DOI: https://doi.org/10.1109/access.2024.3380479
[2024] Toward Improving Ensemble-Based Collaborative Inference at the Edge
DOI: https://doi.org/10.1109/access.2024.3351308
[2024] Efficient Stereo Visual Odometry on FPGA Featuring On-Chip Map Management and Pipelined Descriptor-Based Block Matching
DOI: https://doi.org/10.1109/access.2024.3466238
[2024] Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA
DOI: https://doi.org/10.1109/icce59016.2024.10444323
[2024] A Parallel-Trial Double-Update Annealing Processor for Enabling Highly-Effective Solution Search of Constrained Combinatorial Optimization Problems
DOI: https://doi.org/10.1109/icfpt64416.2024.11113389
[2024] Exploiting N:M Sparsity in Quantized-Folded ResNets: Signed Multicoat Supermasks and Iterative Pruning-Quantization
DOI: https://doi.org/10.1109/candar64496.2024.00036
[2024] WhiteDwarf: 12.24 TFLOPS/W 40 nm Versatile Neural Inference Engine for Ultra-Compact Execution of CNNs and MLPs Through Triple Unstructured Sparsity Exploitation and Triple Model Compression
DOI: https://doi.org/10.1109/a-sscc60305.2024.10849314
[2024] A Flip-Count-Based Dynamic Temperature Control Method for Constrained Combinatorial Optimization by Parallel Annealing Algorithms
DOI: https://doi.org/10.1587/transinf.2024pap0007
[2024] Classical Thermodynamics-based Parallel Annealing Algorithm for High-speed and Robust Combinatorial Optimization
DOI: https://doi.org/10.1145/3638529.3654042
[2024] High Throughput Datapath Design for Vision Permutator FPGA Accelerator
DOI: https://doi.org/10.1109/icce59016.2024.10444339
[2024] ETreeNet: Ensemble Model Fusing Decision Trees and Neural Networks for Small Tabular Data
DOI: https://doi.org/10.1109/ijcnn60899.2024.10651255
[2024] RAW 2024 Invited Talk-5
DOI: https://doi.org/10.1109/ipdpsw63119.2024.00026
[2024] Progressive Variable Precision DNN With Bitwise Ternary Accumulation
DOI: https://doi.org/10.1109/aicas59952.2024.10595894
[2024] Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow
DOI: https://doi.org/10.1109/asp-dac58780.2024.10473865
[2024] Efficient COO to CSR Conversion for Accelerating Sparse Matrix Processing on FPGA
DOI: https://doi.org/10.1109/icce59016.2024.10444348
[2024] An Accurate FPGA-Based ORB Feature Extractor for SLAM with Row-Wise Keypoint Selection
DOI: https://doi.org/10.1109/icce59016.2024.10444305
[2023] Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension
DOI: https://doi.org/10.1109/isscc42615.2023.10067504
[2023] Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision
DOI: https://doi.org/10.1109/access.2023.3347578
[2023] A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations
DOI: https://doi.org/10.1109/mcsoc60832.2023.00077
[2023] Recurrent Residual Networks Contain Stronger Lottery Tickets
DOI: https://doi.org/10.1109/access.2023.3245808
[2023] A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems
DOI: https://doi.org/10.1587/transinf.2023pap0003
[2023] Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge
DOI: https://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185293
[2023] Decision Forest Training Accelerator Based on Binary Feature Decomposition
DOI: https://doi.org/10.1109/fccm57271.2023.00043
[2023] Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance
DOI: https://doi.org/10.1109/coolchips57690.2023.10121990
[2023] A 0.5 V Modified Pseudo-Differential Current-Starved Ring-VCO with Linearity Improvement for IoT Devices
DOI: https://doi.org/10.1109/ieecon56657.2023.10126919
[2023] TT-MLP: Tensor Train Decomposition on Deep MLPs
DOI: https://doi.org/10.1109/access.2023.3240784
[2022] Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet
DOI: https://doi.org/10.1109/isscc42614.2022.9731668
[2022] Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet
[2022] A Hybrid Integer Encoding Method for Obtaining High-quality Solutions of Quadratic Knapsack Problems on Solid-state Annealers
[2022] A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers
DOI: https://doi.org/10.1587/transinf.2022pap0006
[2022] Ring-VCO-based ReLU activation function with linearity improvement for pulsed neuron circuits
DOI: https://doi.org/10.1109/icecs202256217.2022.9970902
[2022] Hiddenite: CNN Inference Accelerator for Randomly Weighted Neural Networks
DOI: https://doi.org/10.7567/ssdm.2022.k-5-01
[2022] Multicoated Supermasks Enhance Hidden Networks
[2022] APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control
DOI: https://doi.org/10.1109/ipdpsw55747.2022.00078
[2021] A Study of Ensemble Learning for Randomly Weighted Neural Network
[2021] Real-Time Tone Mapping: A Survey and Cross-Implementation Hardware Benchmark
DOI: https://doi.org/10.1109/tcsvt.2021.3060143
[2021] Computing Architecture in the Post-Neumann/Post-Moore Era
[2021] ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation
DOI: https://doi.org/10.15803/ijnc.11.2_338
[2021] ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training
DOI: https://doi.org/10.15803/ijnc.11.2_215
[2021] Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks
DOI: https://doi.org/10.5244/c.35.371
[2021] Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture
[2021] A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning
[2021] Linearity Improvement of VCO-Based ADC via Complementary Bias Voltage Control for IoT Devices
DOI: https://doi.org/10.2299/jsp.26.1
[2021] A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning
DOI: https://doi.org/10.1109/icfpt52863.2021.9609699
[2021] Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks
[2021] Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner
DOI: https://doi.org/10.1109/hcs52781.2021.9567328
[2021] Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner
[2021] ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation
[2021] ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training

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AI 要約（直近 5 年の研究成果）

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関連研究室(8 件)

研究成果（63 件）

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所属学会・役職（0 件）