Yoshiki Yamaguchi 研究室

主宰者：Yoshiki Yamaguchi

筑波大学

AI 要約（直近 5 年の研究成果）

要約はまだ生成されていません。

※ AI（Claude）が、公開されている論文要旨から研究の問い・手法・主要な発見を事実情報として抽出・再構成して自動生成しています。誤りを含む可能性があるため、正確性は研究室公式情報でご確認ください。

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研究成果（41 件）

[2026] Low-Latency Streaming for Immersive Remote Interaction with a Spherical Display
DOI: https://doi.org/10.1109/icnc68183.2026.11416943
[2026] Low-Latency FPGA Streaming for Gaze-Based XR Systems on a Spherical Display
DOI: https://doi.org/10.1587/transinf.2026pap0003
[2025] Low-Latency Immersive Display Systems with FPGA for Remote Applications
DOI: https://doi.org/10.1109/ccnc54725.2025.10976057
[2025] Real-Time Recursive Point Cloud Prediction for Interpolating Anomalous Frames
DOI: https://doi.org/10.1109/icce63647.2025.10930093
[2025] Performance review of the prototype SiC muon beam monitor for COMET experiment
DOI: https://doi.org/10.1016/j.nima.2025.170798
[2025] Accelerating CRS Format Conversion for Sparse Matrix Computation with an FPGA
DOI: https://doi.org/10.1109/ipdpsw66978.2025.00195
[2025] PV-VTT: A Privacy-Centric Dataset for Mission-Specific Anomaly Detection and Natural Language Interpretation
DOI: https://doi.org/10.1109/wacv61041.2025.00625
[2025] An adaptive finite-time formation control against actuator attacks in nonlinear singular multiagent systems
DOI: https://doi.org/10.1007/s11071-025-10970-2
[2025] Quantitative Reliability Assessment for 3D LiDAR Point Cloud Data Frames
DOI: https://doi.org/10.1109/icce63647.2025.10929948
[2025] A Method of Detecting Port Bay Numbers and Optimizing Effects Under Various Weather Scenarios
DOI: https://doi.org/10.1109/icce63647.2025.10930172

続きを表示（残り 31 件）

[2024] Enhancing IoT data acquisition efficiency via FPGA-based implementation with OpenCL framework
DOI: https://doi.org/10.1016/j.compeleceng.2024.109830
[2024] Low-latency and high-bandwidth communication using HSS transceivers on a Versal FPGA
DOI: https://doi.org/10.1109/icce59016.2024.10444302
[2024] Qu-Trefoil: Large-Scale Quantum Circuit Simulator Working on FPGA With SATA Storages
DOI: https://doi.org/10.1109/tc.2024.3521546
[2024] A data compressor for FPGA-based state vector quantum simulators
DOI: https://doi.org/10.1145/3665283.3665293
[2024] Systolic Array-Based Many-Core Processor with Simultaneous Dual-Instruction Issuance
DOI: https://doi.org/10.1145/3665283.3665298
[2024] FPGA-Based Improved Background Subtraction for Ultra-Low Latency
DOI: https://doi.org/10.1109/access.2024.3483548
[2024] Scalable dual-instruction multiple-data processing on an efficient systolic-array architecture
DOI: https://doi.org/10.1109/ipdpsw63119.2024.00048
[2024] FPGA-based stereo matching for crop height measurement using monocular camera
DOI: https://doi.org/10.1016/j.micpro.2024.105063
[2024] Stereo Vision System for Crop Height Measurement Using a Monocular Camera-Equipped Drone
DOI: https://doi.org/10.1109/icce59016.2024.10444287
[2024] FPGA-based ultra-low latency background remover
DOI: https://doi.org/10.1109/icce59016.2024.10444168
[2023] Quantitative study of floating-point precision on modern FPGAs
DOI: https://doi.org/10.1145/3597031.3597042
[2023] A cost/power efficient storage system with directly connected FPGA and SATA disks
DOI: https://doi.org/10.1109/mcsoc60832.2023.00016
[2023] A Comparative Study on DRL-Based Autonomous Driving Under Single-Vehicle and Human-Vehicleroad Coordination
DOI: https://doi.org/10.1109/icarce59252.2024.10492530
[2023] A state vector quantum simulator working on FPGAs with extensible SATA storage
DOI: https://doi.org/10.1109/icfpt59805.2023.00041
[2023] Enormous-Scale Quantum State Vector Calculation with FPGA-accelerated SATA storages
DOI: https://doi.org/10.1109/icfpt59805.2023.00049
[2023] GPU Acceleration of Multi-Object Tracking with Motion Vector Interpolation and Affine Transformation
DOI: https://doi.org/10.1109/asap57973.2023.00031
[2023] FPGA-based detector with SiC sensing for real-time monitoring of muon beams
DOI: https://doi.org/10.1145/3597031.3597037
[2023] High-precision plant height measurement by drone with RTK-GNSS and single camera for real-time processing
DOI: https://doi.org/10.1038/s41598-023-32167-6
[2023] GPU–FPGA-accelerated Radiative Transfer Simulation with Inter-FPGA Communication
DOI: https://doi.org/10.1145/3578178.3578231
[2022] Packed SIMD Vectorization of the DRAGON2-CB
DOI: https://doi.org/10.1109/mcsoc57363.2022.00023
[2022] FPGA-based acceleration of stereo matching using OpenCL
DOI: https://doi.org/10.1145/3575882.3575883
[2022] A Scalable Many-core Overlay Architecture on an HBM2-enabled Multi-Die FPGA
DOI: https://doi.org/10.1145/3547657
[2022] Real-Time FPGA Implementation of FIR Filter Using OpenCL Design
DOI: https://doi.org/10.1007/s11265-021-01723-6
[2022] High-Precision Stereo Matching with a Drone Equipped With Rtk-Gnss and a Single Camera for Plant Height Measurements
DOI: https://doi.org/10.2139/ssrn.4053448
[2021] FPGA-Based Implementation of the Stereo Matching Algorithm Using High-Level Synthesis
DOI: https://doi.org/10.1109/mcsoc51149.2021.00009
[2021] An efficient RTL buffering scheme for an FPGA-accelerated simulation of diffuse radiative transfer
DOI: https://doi.org/10.1109/icfpt52863.2021.9609944
[2021] HBM2 Memory System for HPC Applications on an FPGA
DOI: https://doi.org/10.1109/cluster48925.2021.00116
[2021] An FPGA-based storage control with load balancing
DOI: https://doi.org/10.1109/cluster48925.2021.00118
[2021] A study of inter-node communication on a tightly coupled FPGA cluster
[2021] A 64-bit RISC-V many-core architecture on FPGAs
[2021] A Highly-Efficient and Tightly-Connected Many-Core Overlay Architecture
DOI: https://doi.org/10.1109/access.2021.3074171

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所属学会・役職（0 件）

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AI 要約（直近 5 年の研究成果）

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関連研究室(8 件)

研究成果（41 件）

科研費（0 件）

所属学会・役職（0 件）