Cong‐Kha Pham 研究室

主宰者：Cong‐Kha Pham

電気通信大学

AI 要約（直近 5 年の研究成果）

Cong‐Kha Pham研究室では、デジタル回路設計とセキュリティを中心に、実用的で効率的なハードウェア実装に関する研究を行っています。特にRISC-V（オープンソースのプロセッサ命令セット）を基盤とした汎用計算機から、AI処理や暗号化などの特定用途向けハードウェアまで、様々な電子回路の設計と最適化に取り組んでいます。研究対象には、マイクロプロセッサのアーキテクチャ設計、動画圧縮回路、電力変換回路など、幅広い応用分野が含まれています。セキュリティ分野では、量子コンピュータの脅威に対抗するための後量子暗号アルゴリズムのハードウェア実装に注力しています。具体的には、格子暗号などの次世代暗号方式を限られたリソースのIoTデバイスに実装する方法を研究しており、多項式演算を高速化する数論変換(NTT)などの効率的な計算手法を開発しています。同時に、暗号ハードウェアへのサイドチャネル攻撃（電力消費やタイミングの変動から情報を盗む攻撃）に対する防御機構の設計も進めており、S-ボックスの動的生成やスプレッド・スペクトラム技術など、複数の対策手法を提案しています。このように同研究室は、安全性と効率性を両立させた実装技術の開発を通じて、将来のセキュアで省電力な情報通信システムの実現に貢献しています。

※ AI（Claude）が、公開されている論文要旨から研究の問い・手法・主要な発見を事実情報として抽出・再構成して自動生成しています。誤りを含む可能性があるため、正確性は研究室公式情報でご確認ください。

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研究成果（61 件）

[2026] Stability- and Safety-Constraint Reinforcement Learning for Pedestrian Avoidance in Occluded Urban Driving
DOI: https://doi.org/10.3390/electronics15143026
[2026] A Resource-Efficient VVC IME Architecture Using Buffered Aggregation and Bubble-Aware Comparison
DOI: https://doi.org/10.1109/les.2026.3694882
[2026] An Overview of Multilevel Co-Design for AI Accelerator: From Fundamentals to the Frontier
DOI: https://doi.org/10.1109/access.2026.3695927
[2026] An Overview of Critical Architectural and Systemic Considerations for Modern RISC-V Development: From Fundamentals to the Frontier
DOI: https://doi.org/10.1109/access.2026.3704965
[2026] Spiking Neural Networks for Log-Based Anomaly Detection: A Survey, Taxonomy, and Roadmap on Energy-Efficient Neuromorphic Log Analysis
DOI: https://doi.org/10.1109/access.2026.3707431
[2026] Model-to-Hardware Co-Design of a Resource-Efficient RISC-V Edge AI SoC for 1D CNN ECG Classification
DOI: https://doi.org/10.1109/les.2026.3708151
[2026] A 10mW 3.2 GHz All-Digital Fractional-N PLL Achieving -120 dBc/Hz In-Band Phase Noise Using a Continuous Time Bandpass Delta-Sigma Time-to-Digital Converter in 180-nm CMOS
DOI: https://doi.org/10.1109/access.2026.3714537
[2025] Countering Side-Channel Attacks With a Dynamic S-Box Based on Affine Transformations and Gold Sequences
DOI: https://doi.org/10.1109/tvlsi.2025.3595897
[2025] A Unified Approach to Strong PUF and TRNG Using Ring Generator for Cryptography
DOI: https://doi.org/10.1109/jiot.2025.3582869
[2025] Buck Converter with Improved Efficiency and Wide Load Range Enabled by Negative Level Shifter and Low-Power Adaptive On-Time Controller
DOI: https://doi.org/10.3390/electronics14122425

続きを表示（残り 51 件）

[2025] Compact 8-Bit S-Boxes Based on Multiplication in a Galois Field GF(24)
DOI: https://doi.org/10.3390/cryptography9020021
[2025] A Timing-Constrained Design Methodology for Radix- 2 k NTT in Polynomial Arithmetic
DOI: https://doi.org/10.1109/tcsi.2025.3570321
[2025] Dynamic S-Boxes Block Cipher for Side-Channel Attack Resistance
DOI: https://doi.org/10.1109/access.2025.3635088
[2025] Early Termination for Integer Motion Estimation via Multi-Level Successive Elimination in Versatile Video Coding
DOI: https://doi.org/10.1109/access.2025.3623123
[2025] An Area-Time Efficient Hardware Architecture for ML-KEM Post-Quantum Cryptography Standard
DOI: https://doi.org/10.1109/access.2025.3579379
[2025] Constructing 8 × 8 S-Boxes with Optimal Boolean Function Nonlinearity
DOI: https://doi.org/10.3390/cryptography9040067
[2025] A Dual-Mode Adaptive Bandwidth PLL for Improved Lock Performance
DOI: https://doi.org/10.3390/electronics14204008
[2025] An Overview of Phase-Locked Loop: From Fundamentals to the Frontier
DOI: https://doi.org/10.3390/s25185623
[2024] Efficient Hardware Implementation of the Lightweight CRYSTALS-Kyber
DOI: https://doi.org/10.1109/tcsi.2024.3443238
[2024] Spread Spectrum-Based Countermeasures for Cryptographic RISC-V SoC
DOI: https://doi.org/10.1109/tvlsi.2024.3444851
[2024] ASIC Implementation of ASCON Lightweight Cryptography for IoT Applications
DOI: https://doi.org/10.1109/tcsii.2024.3483214
[2024] Compact and Low-Latency FPGA-Based Number Theoretic Transform Architecture for CRYSTALS Kyber Postquantum Cryptography Scheme
DOI: https://doi.org/10.3390/info15070400
[2024] A Trusted Execution Environment RISC-V System-on-Chip Compatible with Transport Layer Security 1.3
DOI: https://doi.org/10.3390/electronics13132508
[2024] A High-Performance Non-Indexed Text Search System
DOI: https://doi.org/10.3390/electronics13112125
[2024] Realization of Authenticated One-Pass Key Establishment on RISC-V Micro-Controller for IoT Applications
DOI: https://doi.org/10.3390/fi16050157
[2024] A multimode SHA-3 accelerator based on RISC-V system
DOI: https://doi.org/10.1587/elex.21.20240156
[2024] Accumulator-Based 16-Bit Processor for Wireless Sensor Nodes
DOI: https://doi.org/10.1109/tcsii.2024.3366776
[2024] High-Speed NTT Accelerator for CRYSTAL-Kyber and CRYSTAL-Dilithium
DOI: https://doi.org/10.1109/access.2024.3371581
[2024] Construction of Robust Lightweight S-Boxes Using Enhanced Logistic and Enhanced Sine Maps
DOI: https://doi.org/10.1109/access.2024.3396452
[2024] High-Efficiency Multi-Standard Polynomial Multiplication Accelerator on RISC-V SoC for Post-Quantum Cryptography
DOI: https://doi.org/10.1109/access.2024.3520592
[2024] A Novel ECG Signal Quality Index Method Based on Skewness-MODWT Analysis
DOI: https://doi.org/10.1109/access.2024.3401708
[2024] Hardware Software Co-Design for Multi-Threaded Computation on RISC-V-Based Multicore System
DOI: https://doi.org/10.1109/access.2024.3505940
[2023] Multi-Functional Resource-Constrained Elliptic Curve Cryptographic Processor
DOI: https://doi.org/10.1109/access.2023.3236406
[2023] A High-Efficiency Modular Multiplication Digital Signal Processing for Lattice-Based Post-Quantum Cryptography
DOI: https://doi.org/10.3390/cryptography7040046
[2023] A Survey of Post-Quantum Cryptography: Start of a New Race
DOI: https://doi.org/10.3390/cryptography7030040
[2023] Electromechanical Modeling and Simulation of MEMS-Based Piezoelectric Vibration Energy Harvesting Device Using PZT-5H Material
DOI: https://doi.org/10.31130/ud-jst.2023.340ict
[2023] Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA
DOI: https://doi.org/10.3390/fi15050186
[2023] Design of a Configurable 4-Channel Analog Front-End for EEG Signal Acquisition on 180nm CMOS Process
DOI: https://doi.org/10.21553/rev-jec.339
[2023] Compacting Side-Channel Measurements With Amplitude Peak Location Algorithm
DOI: https://doi.org/10.1109/tvlsi.2023.3339810
[2023] Transition Factors of Power Consumption Models for CPA Attacks on Cryptographic RISC-V SoC
DOI: https://doi.org/10.1109/tc.2023.3262926
[2022] A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment
DOI: https://doi.org/10.1016/j.compeleceng.2022.108546
[2022] ChaCha20–Poly1305 Authenticated Encryption with Additional Data for Transport Layer Security 1.3
DOI: https://doi.org/10.3390/cryptography6020030
[2022] Low-Cost Area-Efficient FPGA-Based Multi-Functional ECDSA/EdDSA
DOI: https://doi.org/10.3390/cryptography6020025
[2022] A Unified PUF and Crypto Core Exploiting the Metastability in Latches
DOI: https://doi.org/10.3390/fi14100298
[2022] Systems on a Chip With 8 and 32 Bits Processors in 0.18-μm Technology for IoT Applications
DOI: https://doi.org/10.1109/tcsii.2022.3161494
[2022] Trusted Execution Environment Hardware by Isolated Heterogeneous Architecture for Key Scheduling
DOI: https://doi.org/10.1109/access.2022.3169767
[2022] A Robust and Healthy Against PVT Variations TRNG Based on Frequency Collapse
DOI: https://doi.org/10.1109/access.2022.3167690
[2022] A Unified NVRAM and TRNG in Standard CMOS Technology
DOI: https://doi.org/10.1109/access.2022.3193639
[2022] Low Complexity Correlation Power Analysis by Combining Power Trace Biasing and Correlation Distribution Techniques
DOI: https://doi.org/10.1109/access.2022.3150833
[2022] Design of a Low-Power and Low-Area 8-Bit Flash ADC Using a Double-Tail Comparator on 180 nm CMOS Process
DOI: https://doi.org/10.3390/s23010076
[2022] On the performance of non‐profiled side channel attacks based on deep learning techniques
DOI: https://doi.org/10.1049/ise2.12102
[2021] A Fully Digital True Random Number Generator With Entropy Source Based in Frequency Collapse
DOI: https://doi.org/10.1109/access.2021.3099534
[2021] A Real-Time Cache Side-Channel Attack Detection System on RISC-V Out-of-Order Processor
DOI: https://doi.org/10.1109/access.2021.3134256
[2021] Correlation Power Analysis Attack Resisted Cryptographic RISC-V SoC With Random Dynamic Frequency Scaling Countermeasure
DOI: https://doi.org/10.1109/access.2021.3126703
[2021] Exploiting the Back-Gate Biasing Technique as a Countermeasure Against Power Analysis Attacks
DOI: https://doi.org/10.1109/access.2021.3057369
[2021] High-Performance FPGA-Based BWA-MEM Accelerator
DOI: https://doi.org/10.18178/ijmlc.2021.11.3.1044
[2021] Convergence of 5G Technologies, Artificial Intelligence and Cybersecurity of Networked Societies for the Cities of Tomorrow
DOI: https://doi.org/10.1007/s11036-021-01778-6
[2021] An Obstacle Avoidance Two-Wheeled Self-Balancing Robot
DOI: https://doi.org/10.18178/ijmerr.11.1.1-7
[2021] A trigonometric hardware acceleration in 32-bit RISC-V microcontroller with custom instruction
DOI: https://doi.org/10.1587/elex.18.20210266
[2021] A proposal for enhancing training speed in deep learning models based on memory activity survey
DOI: https://doi.org/10.1587/elex.18.20210252
[2021] A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications
DOI: https://doi.org/10.1109/tcsii.2021.3090102

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AI 要約（直近 5 年の研究成果）

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関連研究室(8 件)

研究成果（61 件）

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