Ruilin Zhang 研究室

主宰者：Ruilin Zhang

京都大学

AI 要約（直近 5 年の研究成果）

Zhang研究室は、エネルギー効率が極めて高い超低消費電力電子回路の設計と実装に従事しています。IoTセンサーや宇宙衛星などの資源制約が厳しい環境での動作を想定し、ミリワットからピコワット（1兆分の1ワット）レベルの消費電力を実現する回路設計技術を開発しています。これらの回路は最新の半導体プロセス技術（7ナノメートルから130ナノメートル）を活用し、チップサイズも最小限に抑えられています。主な研究テーマは、人工知能の処理を省電力で実行する専用プロセッサの開発、放射線環境での信頼性確保、および生体内センサーなどの医療応用を支えるマイクロ回路の実装です。さらに、ハードウェア乱数生成器やセキュリティ機能、エネルギーハーベスティング（環境から電力を回収）技術など、限られた電力源で安全に動作するシステムの実現に取り組んでいます。メモリアクセスの最適化やデータ処理の効率化も重要な研究課題となっており、実験的な検証を通じて設計手法の実用性を実証しています。

※ AI（Claude）が、公開されている論文要旨から研究の問い・手法・主要な発見を事実情報として抽出・再構成して自動生成しています。誤りを含む可能性があるため、正確性は研究室公式情報でご確認ください。

外部リンク

研究成果（29 件）

[2026] Frieren: A Fault-Tolerant Reconfigurable Energy-Efficient Computing Architecture With Enhanced Reliability in Harsh Environments
DOI: https://doi.org/10.1109/tc.2026.3688989
[2026] Evaluation of multi-modal vortex-induced vibrations of damped cables using an experimentally tailored wake oscillator model
DOI: https://doi.org/10.1016/j.jweia.2026.106415
[2026] Three-dimensional nonlinear coupled galloping of lamp-attached stay cables: quasi-steady analysis and unsteady experiments
DOI: https://doi.org/10.1007/s11071-025-11947-x
[2026] A 22-nm End-to-End Edge–AI Processor With Booth-Value-Confined Acceleration and Hardware-Aware Layer-Wise Model Deployment
DOI: https://doi.org/10.1109/tvlsi.2026.3701365
[2025] A 22nm CMOS 0.017mm 2 0.9V 0.26nW-Standby-Power 2.7mW-Peak-Power 37GHz Biocompatibly-Covered Ingestible OOK Transmitter Enabling 1cm Communication Via Simulated Large Intestine Model for Digital Pills
DOI: https://doi.org/10.1109/icecs66544.2025.11270639
[2025] Entropy Improvement in Latch-Based True Random Number Generator Using Negative Bias Temperature Instability
DOI: https://doi.org/10.1109/tcsi.2025.3621604
[2025] A 65nm 0.0736mm 2 /Pixel Simultaneous Energy-Harvesting-and-Sensing 2-by-2 Self-Powered CMOS Image Sensor Pixel Array Using Self-Oscillating Voltage Doubler for Thermal-Aware Zero-Stand-by-Power Imaging
DOI: https://doi.org/10.1109/apccas67402.2025.11377210
[2025] A $110-\text{mV} 12-\text{pW} 0.00006-\text{mm}^{2} 7-\text{nm}$ FinFET Self-Oscillating Voltage Doubler Using Vertically Implemented Back-End Metal-Oxide-Metal Capacitors for Small-Formfactor Up-Conversion
DOI: https://doi.org/10.1109/mwscas53549.2025.11244542
[2025] A Scalable External Memory Access and On-Chip Storage Architecture for Edge-AI Accelerators : – Multi-Path Rolling Data Refresh and Layer-Wise Bank Allocation –
DOI: https://doi.org/10.1109/islped65674.2025.11261804
[2025] Design and Experimental Verification of 0.9-2.6pW 0.1-0.25V 22nm 2-Bit Supply-to-Digital Converter Using Always-Activated Supply-Controlled Oscillator and Supply-Dependent-Activation Buffers for Bio-Fuel-Cell-Powered-and-Sensed Time-Stamped Bio-Recording
DOI: https://doi.org/10.1109/tcsii.2025.3590168

続きを表示（残り 19 件）

[2025] A 65-nm CMOS Downconverter-Less Clock Generator Architecture Using Voltage Stacking of Oscillator and Frequency Dividers for Scaling-Friendly IoTs
DOI: https://doi.org/10.1109/tvlsi.2025.3583337
[2025] A 0.071pJ/Bit Flexible Multi-Mode Logic-Compatible Multiple-Time Programmable (MTP) Memory-Based PUF
DOI: https://doi.org/10.1109/tcsii.2025.3574130
[2025] A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-on-Chip Towards In-Orbit Computing
DOI: https://doi.org/10.1109/cicc63670.2025.10983627
[2025] HachiFI: A Lightweight SoC Architecture-Independent Fault-Injection Framework for SEU Impact Evaluation
DOI: https://doi.org/10.23919/date64628.2025.10993139
[2025] A 22 nm CMOS 0.034 mm2 0.4 V 1.3 nW Frequency-Recording IC with 400-Bit Data-Storing Shift Registers Using Burst-Pulse Counting and Reference Pulse Generation for Stand-Alone Continuous Glucose Monitoring Contact Lenses
DOI: https://doi.org/10.1109/lascas64004.2025.10966300
[2025] Design of 0.9-2.6pW 0.1-0.25V 22nm 2-bit Supply-to-Digital Converter Using Always-Activated Supply-Controlled Oscillator and Supply-Dependent-Activation Buffers for Bio-Fuel-Cell-Powered-and-Sensed Time-Stamped Bio-Recording
DOI: https://doi.org/10.1145/3658617.3698492
[2024] A 115mV 300fW 0.24Hz 0.00012 $\text{mm}^{2}$ Schmitt-Trigger Ring Oscillator Using Dynamic Leakage Suppression with Cold Start Capability in 22nm CMOS
DOI: https://doi.org/10.1109/icecs61496.2024.10848622
[2024] A 0.00027 mm2 1.2V 0.089pJ/bit 10Gbps 41.6 GHz Standard-Cell-Based Passive-Less Wireless OOK Transmitter with On-Chip Antenna in 12nm FinFET
DOI: https://doi.org/10.1109/norcas64408.2024.10752439
[2024] A 2 Hz, 1.2-2 V, 0.22-9 nW, 0.007 mm2 65 nm CMOS Multiple- Output Down-Converter-Less Clock Generator Using Stacked an Oscillator and Frequency Dividers for Scaling-Friendly IoTs
DOI: https://doi.org/10.1109/norcas64408.2024.10752488
[2024] De-Correlation and De-Bias Post-Processing Circuits for True Random Number Generator
DOI: https://doi.org/10.1109/tcsi.2024.3421663
[2024] A 0.9-2.6pW 0.1-0.25V 22nm 2-bit Supply-to-Digital Converter Using Always-Activated Supply-Controlled Oscillator and Supply-Dependent-Activation Buffers for Bio-Fuel-Cell-Powered-and-Sensed Time-Stamped Bio-Recording
DOI: https://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631372
[2024] A Latch-Based Stochastic Number Generator for Stochastic Computing of Extended Naïve Bayesian Network
DOI: https://doi.org/10.1109/vlsitsa60681.2024.10546408
[2023] A 0.116 pJ/bit Latch-Based True Random Number Generator Featuring Static Inverter Selection and Noise Enhancement
DOI: https://doi.org/10.1109/tvlsi.2023.3328602
[2023] Practical Markov Chain and Von Neumann based Post-processing Circuits for True Random Number Generators
DOI: https://doi.org/10.1109/mwscas57524.2023.10406056
[2023] A Single-Inverter-Based True Random Number Generator with On-Chip Clock-Tuning-Based Entropy Calibration Circuit
DOI: https://doi.org/10.1587/transfun.2023kep0011
[2022] A 0.186-pJ per Bit Latch-Based True Random Number Generator Featuring Mismatch Compensation and Random Noise Enhancement
DOI: https://doi.org/10.1109/jssc.2021.3137312
[2021] A practical method for predicting post-flutter behavior of a rectangular section
DOI: https://doi.org/10.1016/j.jweia.2021.104707
[2021] A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise Enhancement
DOI: https://doi.org/10.23919/vlsicircuits52068.2021.9492474
[2021] Energy-Efficient Post-Processing Technique Having High Extraction Efficiency for True Random Number Generators
DOI: https://doi.org/10.1587/transele.2020cdp0006

科研費（0 件）

まだデータがありません（KAKEN 取り込み後に表示）。

所属学会・役職（0 件）

まだデータがありません（学会データ連携後に表示）。

AI 要約（直近 5 年の研究成果）

外部リンク

関連研究室(8 件)

研究成果（29 件）

科研費（0 件）

所属学会・役職（0 件）