Tadahiro Kuroda 研究室

主宰者：Tadahiro Kuroda

東京大学

AI 要約（直近 5 年の研究成果）

本研究室は、電子機器の省電力化と高速化を実現するための半導体デバイスおよびシステム設計に関する研究を展開しています。主な研究テーマは、複数のチップを立体的に積み重ねる3次元集積回路（3D-IC）技術と、人工知能処理を効率的に行う専用プロセッサの開発です。3D-ICでは、チップ間の熱を効果的に放散させるため、高い熱伝導率を持つ新規材料の薄膜化と積層化に関する材料・プロセス技術を研究しています。また、チップ同士の接合方法や無線通信インターフェースの開発も進めています。深層学習などの人工知能タスクを低消費電力で実行するプロセッサ設計では、従来のコンピュータアーキテクチャ（メモリと演算素子が分離した構造）の効率性の限界を克服するため、配線の一部が計算回路として機能する「ワイヤロジック」という独自の設計手法を採用しています。さらに、不要な演算を削減するニューラルネットワークの工夫や、FPGA（再構成可能なハードウェア）での効率的な実装方法も開発しており、バッテリー駆動の小型IoT機器から高精度なAIシステムまで、幅広いアプリケーションに対応する低消費電力デバイスの実現を目指しています。

※ AI（Claude）が、公開されている論文要旨から研究の問い・手法・主要な発見を事実情報として抽出・再構成して自動生成しています。誤りを含む可能性があるため、正確性は研究室公式情報でご確認ください。

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研究成果（46 件）

[2025] Aluminum Nitride Interlayer Dielectric Integration for Effective Heat Dissipation of 3D-IC
DOI: https://doi.org/10.1109/iitc66087.2025.11075452
[2025] AlN Gap-Fill Process by Aerosol Deposition Method for Application in 3D-IC Packaging
DOI: https://doi.org/10.1109/ectc51687.2025.00024
[2025] Deposition and integration of aluminum nitride as interlayer dielectric for heat dissipation of 3D-ICs
DOI: https://doi.org/10.1116/6.0004966
[2025] A 78% Area-Reduction in Edge-Coupled Inductive Coupling Link for Flexible Chip Assembly Using Oblong Coil
DOI: https://doi.org/10.7567/ssdm.2025.f-3-03
[2024] Slashing IC Power and Democratizing IC Access for the Digital Age
DOI: https://doi.org/10.2197/ipsjtsldm.17.2
[2024] Agile-X: A Structured-ASIC Created With a Mask-Less Lithography System Enabling Low-Cost and Agile Chip Fabrication
DOI: https://doi.org/10.1109/tvlsi.2024.3486239
[2024] Introduction of thick AlN coating on Si for 3D-IC thermal management
DOI: https://doi.org/10.35848/1347-4065/ad94fa
[2024] A 28-nm 0.8M-weights/mm2 9.1-TOPS/mm2 SRAM-Based All-Analog Compute-In-Memory Using Fine-Grained Structured Pruning with Adaptive-Ranging ADC
DOI: https://doi.org/10.1109/esserc62670.2024.10719563
[2024] Introduction of thick AlN coating on Si for 3D-IC thermal management
DOI: https://doi.org/10.7567/ssdm.2024.c-5-04
[2024] Efficient FPGA Resource Utilization in Wired-Logic Processors Using Coarse and Fine Segmentation of LUTs for Non-Linear Functions
DOI: https://doi.org/10.1109/iscas58744.2024.10558064

続きを表示（残り 36 件）

[2023] Analysis and Design of a 7 Gb/s Rotatable Non-contact Connector with Grid Array Package Application
DOI: https://doi.org/10.1109/newcas57931.2023.10198091
[2023] A 10.7-µJ/Frame 88% Accuracy CIFAR-10 Single-Chip Neuromorphic Field-Programmable Gate Array Processor Featuring Various Nonlinear Functions of Dendrites in the Human Cerebrum
DOI: https://doi.org/10.1109/mm.2023.3315676
[2023] A Deep Metric Learning-Based Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion
DOI: https://doi.org/10.1109/ojies.2023.3284014
[2023] A 12.8-Gb/s 0.5-pJ/b Encoding-Less Inductive Coupling Interface Achieving 111-GB/s/W 3D-Stacked SRAM in 7-nm FinFET
DOI: https://doi.org/10.1109/lssc.2023.3252607
[2023] A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS
DOI: https://doi.org/10.1145/3566097.3567941
[2023] Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS
DOI: https://doi.org/10.1109/tcsi.2023.3268772
[2023] A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network
DOI: https://doi.org/10.1109/iscas46773.2023.10181427
[2023] Hydrophilic Bonding of SiO2/SiO2 and Cu/Cu using Sequential Plasma Activation
DOI: https://doi.org/10.1149/ma2023-02331595mtgabs
[2023] A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA
DOI: https://doi.org/10.1587/transele.2023lhp0001
[2023] A183.4-nJ/Inference 152.8-μW 35-Voice Commands Recognition Wired-Logic Processor Using Algorithm-Circuit Co-Optimization Technique
DOI: https://doi.org/10.1109/lssc.2023.3334625
[2023] Hydrophilic Bonding of SiO2/SiO2 and Cu/Cu using Sequential Plasma Activation
DOI: https://doi.org/10.1149/11203.0095ecst
[2022] A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA using Non-Linear Neural Network
DOI: https://doi.org/10.1109/hcs55958.2022.9895600
[2022] A Low-power RFID with 100kbps Data Rate Employing High-speed Power Clock Generator for Complementary Pass-transistor Adiabatic Logic
DOI: https://doi.org/10.1109/icecs202256217.2022.9971064
[2022] A 1.2nJ/Classification 2.4mm2 Wired-Logic Neuron Cell Array Using Logically Compressed Non-Linear Function Blocks in 0.18undefinedm CMOS
DOI: https://doi.org/10.7567/ssdm.2022.k-5-02
[2022] 3D-Stacked SRAM Using Near-Field Wireless Communication
DOI: https://doi.org/10.5104/jiep.25.549
[2022] 1.2 nJ/classification 2.4 mm2 asynchronous wired-logic DNN processor using synthesized nonlinear function blocks in 0.18 μm CMOS
DOI: https://doi.org/10.35848/1347-4065/acac38
[2022] A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver
DOI: https://doi.org/10.1109/jssc.2022.3224421
[2022] A 12.8-Gbps 0.5-pJ/b Encoding-less Inductive Coupling Interface Using Clocked Hysteresis Comparator for 3D-stacked SRAM in 7-nm FinFET
DOI: https://doi.org/10.1109/a-sscc56115.2022.9980775
[2022] A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers
DOI: https://doi.org/10.1109/hcs55958.2022.9895622
[2022] Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format
DOI: https://doi.org/10.1109/newcas52662.2022.9842091
[2022] A bonding-less 5-GHz RFID module using inductive coupling between IC and antenna
DOI: https://doi.org/10.35848/1347-4065/ac4ce2
[2022] A 5.2GHz RFID Chip Contactlessly Mountable on FPC at any 90-Degree Rotation and Face Orientation
DOI: https://doi.org/10.1109/asp-dac52403.2022.9712597
[2022] mmWave-YOLO: A mmWave Imaging Radar-Based Real-Time Multiclass Object Recognition System for ADAS Applications
DOI: https://doi.org/10.1109/tim.2022.3176014
[2022] A 5-GHz 0.15-mm² Collision-Avoiding RFID Employing Complementary Pass-Transistor Adiabatic Logic With an Inductively Connected External Antenna in 0.18-μm CMOS
DOI: https://doi.org/10.1109/lssc.2022.3223079
[2022] Proximity Wireless Communication Technologies: An Overview and Design Guidelines
DOI: https://doi.org/10.1109/tcsi.2022.3210200
[2021] Sub-10-μm Coil Design for Multi-Hop Inductive Coupling Interface
DOI: https://doi.org/10.1145/3394885.3431649
[2021] A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOS
DOI: https://doi.org/10.1145/3394885.3431642
[2021] An on-chip antenna with an area of 0.9 square millimeters for RFID applications in the 5.8 GHz – 24 GHz range
DOI: https://doi.org/10.23919/isap47053.2021.9391369
[2021] CA2 area detection from hippocampal microscope images using deep learning
DOI: https://doi.org/10.1109/mwscas47672.2021.9531735
[2021] A 0.61-μJ/Frame Pipelined Wired-logic DNN Processor in 16-nm FPGA Using Convolutional Non-Linear Neural Network
DOI: https://doi.org/10.1109/ojcas.2021.3137263
[2021] A Physical Verification Methodology for 3D-ICs Using Inductive Coupling
DOI: https://doi.org/10.1109/edaps53774.2021.9657043
[2021] A 5-GHz 0.15-mm2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna
DOI: https://doi.org/10.1109/a-sscc53895.2021.9634815
[2021] A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System
DOI: https://doi.org/10.1587/transfun.2021vlp0001
[2021] A 16 nJ/Classification FPGA-Based Wired-Logic DNN Accelerator Using Fixed-Weight Non-Linear Neural Net
DOI: https://doi.org/10.1109/jetcas.2021.3114179
[2021] A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC
DOI: https://doi.org/10.1109/jssc.2021.3108820
[2021] A bonding-less 5-GHz RFID module using a 300um x 500um IC chip
DOI: https://doi.org/10.7567/ssdm.2021.l-2-04

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AI 要約（直近 5 年の研究成果）

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関連研究室(8 件)

研究成果（46 件）

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