Takahiro Hanyu 研究室

主宰者：Takahiro Hanyu

東北大学

AI 要約（直近 5 年の研究成果）

本研究室は、不安定な電力供給下で計算を継続するための低消費電力型ハードウェア設計に取り組んでいます。磁気トンネル接合素子という磁性デバイスを活用し、電源が遮断されても情報を保持できる非揮発性レジスタやメモリ回路の開発を進めています。これらのデバイスの特性を活かし、バックアップに必要なエネルギーや回路面積を削減する設計手法を提案・実装しており、間欠的な電力供給環境でのセンサーノードやエッジコンピューティングの実現を目指しています。同時に、確率的計算という新しい計算パラダイムの研究にも注力しています。確率ビットと呼ばれる素子を用いた焼きなまし法のハードウェア化や、古典計算で量子焼きなまし的な動作を模擬する手法を開発しています。これらは組み合わせ最適化問題の高速解法に応用されており、ハードウェア・シミュレーション・アルゴリズムの統合的な設計が特徴です。さらに、エッジデバイス向けの機械学習ハードウェアの設計にも取り組んでいます。小型FPGA上で少量学習や物体検出を実行するシステムの構築、固定小数点演算の精度と効率のバランスを取った量子化手法の開発、電力管理や電力遮断技術による消費電力削減など、実装レベルでの最適化を実現しています。

※ AI（Claude）が、公開されている論文要旨から研究の問い・手法・主要な発見を事実情報として抽出・再構成して自動生成しています。誤りを含む可能性があるため、正確性は研究室公式情報でご確認ください。

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研究成果（56 件）

[2026] Energy- and Area-Efficient MTJ-Based Nonvolatile Register With a Differential Information Storing Scheme
DOI: https://doi.org/10.1109/access.2026.3685082
[2026] Energy-Efficient p-bit-Based Fully-Connected Quantum-Inspired Simulated Annealer With Dual BRAM Architecture
DOI: https://doi.org/10.1109/access.2026.3651741
[2025] Reference-Load Sharing Scheme: An Area- and Energy-Efficient Nonvolatile Register Design Using MTJ Devices
DOI: https://doi.org/10.1109/jxcdc.2025.3611365
[2025] Design of an FPGA-based emulator for rapidly prototyping a nonvolatile system-on-a-chip
DOI: https://doi.org/10.35848/1347-4065/adba6d
[2025] Design of an Intermittent-Computing-Oriented Nonvolatile Register With a Switching-Probability-Aware Store-and-Verify Scheme
DOI: https://doi.org/10.1109/access.2025.3546590
[2025] Intelligent Power-Gating Technique with Quick Wake-Up/Sleep Functionality for Spintronics-Based Edge Computing Hardware
DOI: https://doi.org/10.1109/ismvl64713.2025.00011
[2025] Generating Hamiltonians with Known Minimum Energy Based on Ground-State Spin Logic for Probabilistic-Bit-Based Simulated Annealing
DOI: https://doi.org/10.1109/ismvl64713.2025.00025
[2025] Implementation of an MRAM-Based Edge AI Hardware with a Fine-Grained Power-Gating Technique
DOI: https://doi.org/10.1109/ismvl64713.2025.00010
[2025] An FPGA-based rapid-prototyping platform for spintronics-based edge-computing hardware
DOI: https://doi.org/10.1109/ismvl64713.2025.00023
[2025] A Study on Fault Prediction and Redundancy Control of Parallel SiC-MOSFETs
DOI: https://doi.org/10.23919/ispsd62843.2025.11117383

続きを表示（残り 46 件）

[2025] Design of a Low-Energy MTJ-Based Nonvolatile Register Based on a Differential Information Storing Scheme
DOI: https://doi.org/10.1109/iscas56072.2025.11043267
[2025] Bit-Width-Aware Design Environment for Few-Shot Learning on Edge AI Hardware
DOI: https://doi.org/10.1109/iscas56072.2025.11044227
[2025] GPU-accelerated simulated annealing based on p-bits with real-world device-variability modeling
DOI: https://doi.org/10.1038/s41598-025-90520-3
[2025] Emerging trends in MTJ-based nonvolatile logic circuits toward a revolution in computer architecture
DOI: https://doi.org/10.35848/1347-4065/ae268d
[2025] Emerging Trends in MTJ-Based Nonvolatile Logic LSI Technology
DOI: https://doi.org/10.7567/ssdm.2025.b-2-01
[2025] Design of a single-capacitor-based threshold-adjustable power management circuit for task-aware waste-minimized energy harvesting
DOI: https://doi.org/10.1587/elex.22.20250395
[2024] Design of a High-Speed and Low-Power Threshold Adjustment Unit for Battery-Free Edge Devices
DOI: https://doi.org/10.1109/ijcnn60899.2024.10651524
[2024] Individual Control of Paralleled SiC-MOSFETs with Nano-Second Level Switching Timing Synchronization
DOI: https://doi.org/10.1109/ispsd59661.2024.10579615
[2024] Design of a spin–orbit-torque-based self-terminated nonvolatile register for a write/leakage-energy-minimized backup operation
DOI: https://doi.org/10.35848/1347-4065/ad2a9c
[2024] Stochastic Simulated Quantum Annealing for Fast Solution of Combinatorial Optimization Problems
DOI: https://doi.org/10.1109/access.2024.3431540
[2024] Enhanced convergence in p-bit based simulated annealing with partial deactivation for large-scale combinatorial optimization problems
DOI: https://doi.org/10.1038/s41598-024-51639-x
[2024] Error-Tolerant Quantized Neural Network Based on Non-Weighted Arithmetic
DOI: https://doi.org/10.1109/ismvl60454.2024.00019
[2024] Design of an Energy/Area-Aware MTJ-Based Nonvolatile Register with a Reference-Load Sharing Scheme
DOI: https://doi.org/10.1109/mwscas60917.2024.10658712
[2024] Design Environment of Quantization-Aware Edge AI Hardware for Few-Shot Learning
DOI: https://doi.org/10.1109/mwscas60917.2024.10658789
[2023] Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing
DOI: https://doi.org/10.1109/jetcas.2023.3243260
[2023] High-Performance/Low-Area Power-Gating Switch Linear Array for Energy-Efficient LSIs with an Optimum Switch-Timing Control
DOI: https://doi.org/10.1109/iscas46773.2023.10181350
[2023] Write-Energy Relaxation of MTJ-Based Quantized Neural-Network Hardware
DOI: https://doi.org/10.1109/ismvl57333.2023.00013
[2023] Design of a nonvolatile-register-embedded RISC-V CPU with software-controlled data-retention and hardware-acceleration functions
DOI: https://doi.org/10.1016/j.memori.2023.100035
[2023] Design of an energy-efficient nonvolatile lookup table circuit using active-load-localized circuitry with self-terminated writing/reading
DOI: https://doi.org/10.35848/1347-4065/acbd5a
[2023] Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing
DOI: https://doi.org/10.1109/ojsp.2023.3329756
[2023] Self-Adaptive Gate Control for Efficient Escape From Local Minimum Energy on Invertible Logic
DOI: https://doi.org/10.1109/access.2023.3272867
[2023] Stochastic Implementation of Simulated Quantum Annealing on PYNQ
DOI: https://doi.org/10.1109/icfpt59805.2023.00042
[2023] Error-Sensitivity-Aware Write-Energy Optimization for an MTJ-Based Binarized Neural Network
DOI: https://doi.org/10.1109/icecs58634.2023.10382768
[2023] Improving Stochastic Quantum-Like Annealing Based on Rerandomization
DOI: https://doi.org/10.1109/icecs58634.2023.10382735
[2023] Design of an SOT-Based Self-Terminated Nonvolatile Register for Write/Leakage-Energy-Minimized Backup Operation
DOI: https://doi.org/10.7567/ssdm.2023.j-5-02
[2023] Impact of Spintronics-Based Nonvolatile Hardware for AI Applications
DOI: https://doi.org/10.7567/ssdm.2023.j-5-01
[2023] Design of an Error-Tolerant Nonvolatile Register for Energy-Aware Intermittent Computing
DOI: https://doi.org/10.1109/mwscas57524.2023.10405935
[2022] Design of an active-load-localized single-ended nonvolatile lookup-table circuit for energy-efficient binary-convolutional-neural-network accelerator
DOI: https://doi.org/10.35848/1347-4065/ac51bf
[2022] Fast Solving Complete 2000-Node Optimization Using Stochastic-Computing Simulated Annealing
DOI: https://doi.org/10.1109/icecs202256217.2022.9971124
[2022] Energy-Efficient Nonvolatile RISC-V CPU with a Custom Instruction-Controlled Accelerator
DOI: https://doi.org/10.1109/mwscas54063.2022.9859466
[2022] Design of an Energy-Efficient Nonvolatile Lookup Table Circuit Using Active-Load-Localized Circuitry with Self-Terminated Writing/Reading
DOI: https://doi.org/10.7567/ssdm.2022.k-5-04
[2022] A Spintronics-Based Nonvolatile FPGA and Its Application to Edge-AI Accelerator
DOI: https://doi.org/10.1109/mcsoc57363.2022.00018
[2021] Dynamic activation of power-gating-switch configuration for highly reliable nonvolatile large-scale integrated circuits
DOI: https://doi.org/10.35848/1347-4065/ac461a
[2021] CMOS Invertible Logic: Bidirectional operation based on the probabilistic device model and stochastic computing
DOI: https://doi.org/10.1109/mnano.2021.3126094
[2021] A Memory-Access-Minimized BCNN Accelerator Using Nonvolatile FPGA with Only-Once- Write Shifting
DOI: https://doi.org/10.1109/mcsoc51149.2021.00021
[2021] Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices
DOI: https://doi.org/10.1109/sips52927.2021.00047
[2021] Dynamic Power-Gating-Switch Control Technique and Its Application to an Energy-Efficient Embedded STT-MRAM
DOI: https://doi.org/10.7567/ssdm.2021.l-1-02
[2021] Design of an Energy-Efficient Nonvolatile-FPGA-Based BCNN Accelerator Using an Active-Load-Localized Single-Ended Circuit Style
DOI: https://doi.org/10.7567/ssdm.2021.l-1-01
[2021] Nonvolatile Field-Programmable Gate Array Using a Standard-Cell-Based Design Flow
DOI: https://doi.org/10.1587/transinf.2020lop0010
[2021] High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians
DOI: https://doi.org/10.1109/iscas51556.2021.9401278
[2021] Design of an energy-efficient binarized convolutional neural network accelerator using a nonvolatile field-programmable gate array with only-once-write shifting
DOI: https://doi.org/10.35848/1347-4065/abe682
[2021] Design automation of invertible logic circuit from a standard hdl description
[2021] Design of a highly reliable nonvolatile flip-flop incorporating a common-mode write error detection capability
DOI: https://doi.org/10.35848/1347-4065/abdcb0
[2021] Sparse Random Signals for Fast Convergence on Invertible Logic
DOI: https://doi.org/10.1109/access.2021.3072048
[2021] Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices
DOI: https://doi.org/10.1109/ojcas.2021.3116584
[2021] Design framework for an energy-efficient binary convolutional neural network accelerator based on nonvolatile logic
DOI: https://doi.org/10.1587/nolta.12.695

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AI 要約（直近 5 年の研究成果）

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研究成果（56 件）

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