Mitsumasa Koyanagi 研究室

AI 要約（直近 5 年の研究成果）

※ AI（Claude）が、公開されている論文要旨から研究の問い・手法・主要な発見を事実情報として抽出・再構成して自動生成しています。誤りを含む可能性があるため、正確性は研究室公式情報でご確認ください。

研究成果（16 件）

• [2025] Die-Level Transformation From 2D Shuttle Chips to 3D-IC With TSV for Advanced Rapid Prototyping Methodology With Meta Bonding
  DOI: https://doi.org/10.1109/jetcas.2025.3572003
• [2023] Copper Electrode Surface Features and Cu-SiO₂Hybrid Bonding
  DOI: https://doi.org/10.1109/3dic57175.2023.10154924
• [2023] Impact of Super-long-throw PVD on TSV Metallization and Die-to-Wafer 3D Integration Based on Via-last
  DOI: https://doi.org/10.1109/3dic57175.2023.10154930
• [2023] Chip-to-Chip Hybrid Bonding with Larger-Oriented Cu Grains for µ-joints Beyond 100 K
  DOI: https://doi.org/10.1109/ectc51909.2023.00292
• [2022] System Integration Technology Based on 3D Integration
  DOI: https://doi.org/10.1109/imfedk56875.2022.9975417
• [2022] Cu-SiO₂ Hybrid Bonding Yield Enhancement Through Cu Grain Enlargement
  DOI: https://doi.org/10.1109/ectc51906.2022.00115
• [2022] Tight-Pitched 10 μm-Width Solder Joints for c-2-c and c-2-w 3D-Integration in NCF Environment
  DOI: https://doi.org/10.1109/ectc51906.2022.00184
• [2022] Comprehensive Study on Advanced Chip on Wafer Hybrid Bonding with Copper/Polyimide Systems
  DOI: https://doi.org/10.1109/ectc51906.2022.00059
• [2021] Implementation of a Chaotic Neural Network Reservoir on a TSV/$\mu\text{Bump}$ Stacked 3D Cyclic Neural Network Integrated Circuit
  DOI: https://doi.org/10.1109/3dic52383.2021.9687614
• [2021] Integration of Damage-less Probe Cards Using Nano-TSV Technology for Microbumped Wafer Testing
  DOI: https://doi.org/10.1109/3dic52383.2021.9687601

科研費（0 件）

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所属学会・役職（0 件）

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